product structure silicon monolithic integrated circuit this product is not designed prot ection against radioactive rays 1/92 tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 14? 001 datashee t 24bit audio codec series 3w+3w class ab/d speaker amp stereo audio codec BU26156RFS general description BU26156RFS is low power stereo audio codecs with built-in various acoustic effects. BU26156RFS has stereo line and monaural mic inputs that can input to 2vrms, stereo speaker amplifier that can change class ab / d and stereo headphone outputs.bu26156 also has built-in voltage regulator for the stability of codec characteristic that is s ensitive to the outside noise. features ? 24bit stereo adc, dac ? 2vrms input available, stereo line input with alc ? monoraul mic input with alc ? switch class ab/d 3w stereo speaker amplifier ? am avoidance function ? stereo headphone output amplifier ? digital signal processing ? high power supply rejection ratio characteristic applications ? radio cassette recorder ? pc speaker important characteristic ? supply voltage splvdd,sprvdd: 2.7v to 5.5v hvdd1: 2.7v to 3.6v hpvdd: 2.7v to 3.6v iovdd: 1.65v to 5.5v ? mic-adc snr: 87[db](typ.) ? line-adc snr: 93[db](typ.) ? dac-sp snr: 86[db](typ.) ? dac-lout snr: 95[db](typ.) ? operating temperature: -20 to +85 package w(typ.) x d(typ.) x h(max.) htssop-a44r 18.50mm x 9.50mm x 1.00mm figure 1. htssop-a44r basic block diagram figure 2.
datasheet datasheet 2/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 pin layout htssop-a44r top view figure 3. pin description no name i/o power function reset no use 25 resetb i iovdd reset pin ?l? level : reset enable. ?h? level : reset disable. (input) - 23 sdata /sda io iovdd 3 wire interface: data input output pin it is indicated as sdata on the description of ac characteristics. 2 wire interface : data input output pin (note1) it is indicated as sda on the description of ac characteristics. (input) - 22 sclk /sad i iovdd 3 wire interface : serial clock input pin it is indicated as sclk on the description of ac characteristics. 2 wire interface: slave address pin future explanation indicates sad. choose from the following two kinds. sad pin=hgnd : ?0011010? (input) dgnd hpoutl hpgnd 3 1 hpoutr 2 hpoutcap 4 nc 5 splvdd splp 8 6 splm 7 splgnd 9 sprgnd 10 sprp sprvdd 13 11 sprm 12 spmute 14 beepin 15 micbias 17 micbiasref 16 hvdd 1 18 agnd 19 regout 20 dgnd 21 hpvdd lin 3l 42 44 lin 3 r 43 lin2 r 41 lin 2l 40 lin 1 r vmid 37 39 lin 1l 38 agnd 36 minp 35 minm mclki 32 34 pllc 33 bclk 31 lrclk 30 sdout 28 sdin 29 iovdd 27 irqb 26 resetb 25 csb/scl 24 sclk/sad 22 sdata/sda 23
datasheet datasheet 3/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 sad pin=iovdd : ?0011011? 24 csb /scl i iovdd 3 wire interface : chip select input pin it is indicated as csb on the description of ac characteristics. 2 wire interface : serial clock input pin (note1) it is indicated as scl on the description of ac characteristics. (input) - 30 lrclk io iovdd sai lr clock input/output pin (input) dgnd 31 bclk io iovdd sai bit clock input/output pin (input) dgnd 29 sdin i iovdd sai serial data input pin (input) dgnd 28 sdout o iovdd sai serial data output pin dgnd open 32 mclki i iovdd master clock pin (input) dgnd 26 irqb o iovdd interrupt output pin iovdd open 38 lin1l i regout line analog input lch pin 1 (input) open, or coupling capacitor connected to agnd near by bu26156 39 lin1r i regout line analog input rch pin 1 (input) 40 lin2l i regout line analog input lch pin 2 (input) 41 lin2r i regout line analog input rch pin 2 (input) 42 lin3l i regout line analog input lch pin 3 (input) 43 lin3r i regout line analog input rch pin 3 (input) 35 minp i regout analog microphone + input (input) 34 minm i regout analog microphone - input (input) 15 beepin i regout line input pin. the input signal for this pin can output headphone output pins or speaker output pins. (input) 16 micbiasref o hvdd1 external filter pin for microphone bias. a capacitor is connected between micbiasref and agnd. angd open 1 micbias o hvdd1 microphone bias voltage output pin a capacitor is connected between micbiascap and agnd. agnd open 37 vmid o regout analog reference voltage pin a capacitor is connected between vmid and agnd. agnd - 20 regout o hvdd1 regulator output pin a capacitor is connected between regout and hgnd1. please put in the chip close as much as possible. agnd - 8 splp o splvdd speaker lch output + pin splgnd open 7 splm o splvdd speaker lch output - pin splgnd open 11 sprp o sprvdd speaker rch output + pin sprgnd open 12 sprm o sprvdd speaker rch output - pin sprgnd open 14 spmute i iovdd test control pin ?l? level : release mute ?h? level : mute dgnd open 1 hpoutl o hpvdd headphone lch output pin hpgnd open 2 hpoutr o hpvdd headphone rch output pin hpgnd open 32 loutcap o hvdd1 headphone ou tput capacitance pin agnd open 33 pllc o regout pll filter pin the width of the clock frequency to input can be expanded. agnd open 27 iovdd p - interface power supply pin a capacitor is connected between iovdd and hgnd1. - - 6 splvdd p - speaker lch power supply pin it is used on the same voltage as sprvdd. a capacitor is connected between splvdd and splgnd. - - 9 splgnd p - speaker lch ground pin - - 13 sprvdd p - speaker rch power supply pin it is used on the same voltage as splvdd. a capacitor is connected between sprvdd and sprgnd. - - 10 sprgnd p - speaker rch ground pin - - 18 hvdd1 p - high voltage power supply 1 pin a capacitor is connected between hvdd1 and hgnd1. - - 19, 36 agnd p - analog ground pin - - 21 dgnd p digital ground pin
datasheet datasheet 4/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 44 hpvdd p headphone power supply pin. a capacitor is connected between hpvdd and hpgnd. 3 hpgnd p headphone ground pin. 5 nc - no connection pin. set open this pin. open (note1)in case of 2 wire serial, if this pin is used with ex ternal pull-up resistor, it possibly gets noise from power. theref ore tamper noise design is required in the noisy environment. application examples figure 4. application examples1(use internal speaker amplifier) figure 5. application examples2 (use external speaker amplifier)
datasheet datasheet 5/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 absolute maxi mum ratings parameter symbol condition rating unit splvdd, sprvdd supply voltage splvdd sprvdd - -0.3 to 7.0 v hpvdd supply voltage hpvdd - -0.3 to 4.5 v hvdd1 supply voltage hvdd1 - -0.3 to 4.5 v iovdd supply voltage iovdd - -0.3 to 7.0 v input voltage v in mclki, lrclk, bclk, sdin, sdata/sda, sclk/sad, csb/scl, spmute -0.3 to iovdd+0.3 v lin1l, lin1r, lin2l, lin2r, minl, minr, beepin -0.3 to regout+0.3 v storage temperature tstg - -55 to +150 c package power dissipation jc htssop-a44r 2 (tjmax=+125 ) /w output current 1 iosp splm, splp, sprm, sprp -1.0 to +1.0 a output current 2 iolo hpoutl, hpoutr -100 to +100 ma output current 3 iorego regout -30 to 0 ma output current 4 ioo all digital pins -8 to +8 ma do not short the output pin to another out put pin, power supply pin or gnd pin. (output pin includes an io pin which is in output mode) caution: operating the ic over the absolute maximum ratings may damage the ic. the damage can either be a short circuit between pins or an open circuit between pins and the internal circuitry. therefore, it is import ant to consider circuit protection measures, such as adding a f use, in case the ic is operated over the absolute maximum ratings. recommended operating condition parameter symbol condition rating unit splvdd, sprvdd supply voltage splvdd sprvdd splvdd=sprvdd 2.7 to 5.5 v hpvdd supply voltage hpvdd - 2.7 to 3.6 v hvdd1 supply voltage hvdd1 - 2.7 to 3.6 v iovdd supply voltage iovdd - 1.65 to 5.5 v operating temperature top - -20 to +85 c *the radiation-proof design is not carried out.
datasheet datasheet 6/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 electrical characteristics dc characteristics (all gnd terminals=0v, hvdd1=3.3v, iovdd= 3.3v, splvdd=sprvdd=hpvdd=3.3v, ta=25c) parameter symbol condit ion min. typ. max. uni t related pin ?h? input voltage 1 vih1 dgnd=0v iovdd0.8 - iovdd+0.3 v resetb, sdata/sda, sclk/sad, csb/scl, spmute and mclki pins. ?h? input voltage 2 vih2 dgnd=0v iovdd0.7 - iovdd+0.3 v lrclk, bclk and sdin pins. ?l? input voltage vil dgnd=0v -0.3 - iovdd0.2 v all digital input ?h? output voltage voh ioh=-1ma iovdd0.85 - - v except sda ?l? output voltage 1 vol1 iol=1ma - - iovdd0.15 v except sda ?l? output voltage 2 vol2 iol=3ma, iovdd R2v iovdd <2v - - - - 0.4 iovdd0.2 v sda ?h? input leakage current 1 iih1 vih= iovdd - - 10 a except spmute ?l? input leakage current iil vil=dgnd -10 - - a all digital input ?z? output leakage current iozh voh=iovdd - - 10 a sda ?z? output leakage current iozl vol=dgnd -10 - - a sda stanby current hvdd1 iddsh1 resetb=?l? - 0.1 10 a splvdd+spr vdd iddssp - 0.1 10 a hpvdd iddshp - 0.1 10 a iovdd iddsio - 0.1 10 a operating current 1, dac mixvol headphone output ( fs48khz, no load, no signal input, sound effect off ) hvdd1 iddo1h1 headphone output, no load, no signal input, sound effect off - 6.2 9.5 ma splvdd+spr vdd iddo1sp - 0.02 0.1 ma hpvdd iddo1hp - 1.0 1.3 ma iovdd iddo1io - 0.03 0.1 ma operating current 2, dac mixvol d-class speaker output ( fs48khz, no load, no signal input, sound effect off ) hvdd1 iddo2h1 d-class speaker output, no load, no signal input, sound effect off - 6.2 8.2 ma splvdd+spr vdd iddo2sp - 3.3 7.4 ma spvdd=3.3v splvdd+spr vdd iddo2sp_5 - 5.0 - ma spvdd=5v hpvdd iddo2hp - 0.03 0.1 ma iovdd iddo2io - 0.03 0.1 ma operating current 3, dac mixvol ab-class speaker output ( fs48khz, no load, no signal input, sound effect off ) hvdd1 iddo3h1 ab-class speaker output, no load, no signal input, sound effect off - 6.2 8.2 ma splvdd+spr vdd iddo3sp - 5.0 9.6 ma spvdd=3.3v splvdd+spr vdd iddo3sp_5 - 6.0 - ma spvdd=5v
datasheet datasheet 7/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 hpvdd iddo3hp - 0.03 0.1 ma iovdd iddo3io - 0.03 0.1 ma operating current 4, micin linemix adc ( fs48khz, sin1khz-full scale input, micbias enable, mic alc off, sound effect off ) hvdd1 iddo4h1 fs48khz, no signal input,, micbias enable, mic alc off, sound effect off - 12.3 16.9 ma splvdd+spr vdd iddo4sp - 0.02 0.1 ma hpvdd iddo4hp - 0.03 0.1 ma iovdd iddo4io - 0.03 0.1 ma operating current 5, linein llinemix adc ( fs48khz, sin1khz-full scale input, linealc off, sound effect off ) hvdd1 iddo5h1 fs48khz, no signal input, line alc off, sound effect off - 11.2 13.8 ma splvdd+spr vdd iddo5sp - 0.02 0.1 ma hpvdd iddo5hp - 0.03 0.1 ma iovdd iddo5io - 0.03 0.1 ma operating power (all gnd terminals=0v, iovdd=3.3v, hvdd1=3.3 v, splvdd=sprvdd=5.0v, hpvdd=3.3v, ta=25c) paramete r symbol condition min typ max unit regulator output regout output level vregout - 1.7 1.8 1.9 v beep input full scale input signal level vbinfs - - - 1 vpp line input ( r lin =22 k ? / line gain=-9db / digital volume=0.0db / line alc=off ) full scale input signal level vlinfs lin1l, lin2l, lin3l, lin1r, lin2r, lin3r - - 2.0 vrms mic input (mic gain=20.25db / digital volume=0.0db / mic alc=off) full scale input signal level vminfs1 minp,minm - - 0.124 vp-p input resistance rmin1 minp,minm 20 30 40 k ? mic input (mic gain=9.0db / digital volume=0.0db / mic alc=off) full scale input signal level vminfs2 minp,minm - - 0.454 vp-p input resistance rmin2 minp,minm 20 30 40 k ? analog reference level (vmid-pin) analog reference voltage vref - 0.9x regout/2 1.0x regout/2 1.1x regout/2 v microphone bias (micbias-pin) output voltage (vmic datasheet datasheet 8/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 power supply rejection ratio psrr1 hvdd1 on 100mvp-p, 1khz ripple, no signal input - 90 - db analog mic inputs to adc out (mic gain=20.25db / line mix gain = 0db / digital volume=0.0db / mic alc=off) s/(n+d) snd2 -1dbfs/ a-weighted - 79 - db s/n snr2 a-weighted - 81 - db power supply rejection ratio psrr2 hvdd1 on 100mvp-p, 1khz ripple, no signal input - 89 - db analog mic inputs to adc out (mic gain=9.0db / digital volu me=0.0db / mic alc=off) s/(n+d) snd3 -1dbfs/ a-weighted - 80 - db s/n snr3 a-weighted - 87 - db power supply rejection ratio psrr3 hvdd1 on 100mvp-p, 1khz ripple, no signal input - 90 - db dac to headphone out (hpoutl/hpoutr, with 220fcuppling 16 ? load) output power po4 thd+n=1%, rl=16 ? - 60 - mw total harmonic distortion thd4 -6dbfs input / a-weighted - 79 - db signal to noise ratio snr4 a-weighted - 90 - db power supply rejection ratio psrr4 hpvdd on 100mvp-p,1khz ripple, no signal input - 60 - db hvdd1 on 100mvp-p,1khz ripple - 80 - db dac to class-ab speaker out (splp/splm, sprp/sprm, with 8 ? / 50pf load ) output power po5-1 spmixg=12db, rl=8 ? ,thd=1% - 1.4 - w po5-2 spmixg=12db, rl=8 ? ,thd=10% - 1.7 - w po5-3 spmixg=12db, rl=4 ? ,thd=1% 1.5 2.5 - w po5-4 spmixg=12db, rl=4 ? ,thd=10% 2 3 - w total harmonic distortion thd5 po=1w, rl=8 ? / a-weighted - 62 - db signal to noise ratio snr5 a-weighted - 91 - db power supply rejection ratio psrr5 splvdd / sprvdd on 100mvp-p,1khz ripple - 60 - db hvdd1 on 100mvp-p,1khz ripple - 80 - db dac to class-d speaker out (splvdd=sprvdd=5v,splp/splm, sprp/sprm, with 8 ? / 50pf load ) output power po6-1 spmixg=12db, rl=8 ? ,thd=1% - 1.4 - w po6-2 spmixg=12db, rl=8 ? ,thd=10% - 1.7 - w po6-3 spmixg=12db, rl=4 ,thd=1% 1.5 2.5 - w po6-4 spmixg=12db, rl=4 ? ,thd=10% 2 3 - w total harmonic distortion thd6 po=1w, rl=8 / a-weighted - 62 - db signal to noise ratio snr6 a-weighted - 89 - db power supply rejection ratio psrr6 splvdd / sprvdd on 100mvp-p,1khz ripple - 72 - db hvdd1 on 100mvp-p,1khz ripple - 80 - db class d oscillator frequency (am avoidance) oscillator frequency am0 ama[1:0]=0b00 360 400 440 khz am1 ama[1:0]=0b01 450 500 550 khz am2 ama[1:0]=0b10 540 600 660 khz
datasheet datasheet 9/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 am3 ama[1:0]=0b11 630 700 770 khz microphone bias (micbias-pin) output noise voltage vmicn7 22hz to 22khz, vmic =1.67 x regout/2 - 5 - v power supply rejection ratio psrr7 hvdd1 on 100mvp-p,1khz ripple load=1ma - 80 - db
datasheet datasheet 10/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 ac characteristics clock pll not use (dgnd=0v, iovdd=3.3v, hvdd1=3.3v,ta=25c) parameter symbol min max. unit mclki frequency fc 2.048m 49.152m hz mclki period tc 1/fc 1/fc s mclki length tch tc*0.4 - s mclki length tcl tc*0.4 - s pll use (external loop back filter not used) (dgnd =0v, iovdd=3.3v, hvdd1=3.3v, ta=25c) parameter symbol min max. unit mclki frequency fc 2m 54m hz mclki period tc 1/fc 1/fc s mclki length tch tc*0.4 - s mclki length tcl tc*0.4 - s pll use (external loop back filter used) (dgnd =0v, iovdd=3.3v, hvdd1=3.3v, ta=25c) parameter symbol min max. unit mclki frequency fc 32k 2m hz mclki period tc 1/fc 1/fc s mclki length tch tc*0.4 - s mclki length tcl tc*0.4 - s mclki tc, fc tch tcl figure 6.
datasheet datasheet 11/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 reset (dgnd =0v, iovdd=3.3v, hvdd1=3.3v, ta=25c) parameter symbol min max. unit resetb pulse width tw_rst 5 - s resetb tw_rst figure 7. when reset pin is made low level, internal ldo is power down mode. it is necessary for 1ms until regout pin becomes low le vel. the recommendation of tw_rst is 1ms over. 2 wire serial interface (dgnd =0v, iovdd=3.3v, hvdd1=3.3v, ta=25c, cl=30pf) parameter symbol standard mode fast mode unit min max. min max. scl frequency f scl - 100 - 400 khz scl ?l? length t low 4.7 - 1.3 - s scl ?h? length t high 4.0 - 0.6 - s hold time under repeat [start] condition t hd:sta 4.0 - 0.6 - s setup time under repeat[start] condition t su:sta 4.0 - 0.6 - s data hold time t hd:dat 0 3.45 0 0.9 s data setup time t su:dat 250 - 100 - ns setup time under [stop] condition t su:sto 4.0 - 0.6 - s figure 8. sda t hd:dat t low t high t su:dat t su:sto t su:st a scl t hd:sta
datasheet datasheet 12/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 3 wire serial interface (dgnd=0v, iovdd=3.3v, hvdd1=3.3v, ta=25c, cl=30pf) parameter symbol min max. unit sclk low to chip select enable tslcl 100 - ns chip select enable to sclk low tclsl 100 - ns chip select enable to sclk high tclsh 100 - ns sclk high to chip select enable tshcl 100 - ns sclk high pulse width tsh 50 - ns sclk low pulse width tsl 50 - ns input data setup time tids 30 - ns input data hold time tidh 30 - ns sclk last edge to chip select disable tchs2 100 - ns chip select high pulse width tch 100 - ns output data valid todv - 40 ns chip select high to data transition tchdts - 40 ns two kinds of timing is supported depends on the sclk pin level at data transfer start. read or write is selected by lsb level of index. figure 9. csb sdata sclk sclk sdata
datasheet datasheet 13/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 serial audio interface (slave) (dgnd=0v, iovdd=3.3v, hvdd1=3.3v, ta=25c, cl=30pf) parameter symbol min max. unit sai_bclk period tc_bclk 32fs 128fs hz sai_bclk ?h? length thw_bclk 73 - ns sai_bclk ?l? length tlw_bclk 73 - ns sai_lrclk hold time th_lrclk 20 - ns sai_lrclk setup time tsu_lrclk 20 - ns sai_sdout delay time td_sdo (note1) - 80 ns sai_sdin setup time tsu_sdi 20 - ns sai_sdin hold time th_sdi 20 - ns (note1) td_sdo is the delay time from later one of sai_bclk transition and sai_lrclk transition. lrclk bclk sdout tc_bclk tsu_lrclk th_lrclk td_sdo thw_bclk tlw_bclk sai transmit figure 10. lrclk bclk sdin tc_bclk tsu_lrclk th_lrclk tsu_sdi th_sdi thw_bclk tlw_bclk sai receive figure 11.
datasheet datasheet 14/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 power supply sequence please power on/off the lsi with all kind of power at the same time. each power supply should power up/down in 50ms.also keep all power supply in the on state or the off state. please avoid partial on or partial off states.don? t have to keep the sequence of power on/off please keep resetb pin ?l? level until all power supply becom e on state. the cpu i/f available when all power supply are powered on, exceed tw_purst, reset are disabled and exceed tw _regu . it is regardless that turn of power on and off of iovdd and hvdd. parameter symbol min typ max unit power on delay time t vdd_on 0 - 50 ms power down delay time t vdd_off 0 - 50 ms reset time after power on t w_purst 1 - - s wait time for regulato r starting after reset release t w_regu 1 - - ms iovdd power suppl y t vdd_on powersupply*0.9 powersupply*0.9 t vdd_off not available available not available cpu i/f resetb other power suppl y vdd off operation vdd off status powerdown wait regulator t w_regu powersupply*0.1 powersupply*0.1 regout t w_purst figure 12.
datasheet datasheet 15/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 function description clock control main modules that make up sound path of the lsi inside operate with 256fs audio clock. audio clock can be selected whether divided clock of 256fs/512fs/1024fs from mclki or generated clock from audio pll. in case of used external loop filter of pll, input clock must be 2mhz to 54mhz frequency. in case of not used external filter of pll, input clock must be 32 khz to 2mhz frequency. it is po ssible to select internal clock either mclki port or lrclk port or bclk port. internal clock is selected clock input/ou tput control register. these frequency mean 512fs and master clock is divided by 2 from pll output when sampling frequency is 16 khz to 24 kh z, and these frequency mean 1024fs and master clock is divided by 4 from pll output when sampling frequency is 8 khz to 12 khz. ?? pll condition setting (changing) sequence 1. stop pll output by setting plloe bit to ?0? 2. disable pll by setting pllen bit to ?0? 3. set fpllm, fppnl, fpllnh, fplld, fpllfl, fpllfh, fpllfdl, fpllfdh 4. set pllen bit to ?1? 5. wait for the pll stabilizing time as the table ?pll stabilizing time? 6. set plloe bit to ?1? 7. start recording or playback. pll stabilizing time pll stabilizing time 10msec - related register sampling rate setting register fpllm, fppnl, fpllnh, fplld, fpllfl, fpllfh, fpllfdl, fpllfdh register clock enable register clock input/output c ontrol register
datasheet datasheet 16/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15? 001 when pll is used. the lsi support audio pll function that ca n generate precise audio clock from wide range of clock frequency. then, it can be realize audio function without external clock gener ator for audio. the lsi supports following cases. case 1: pllisel=0 or 2, mst=0, mclkoe=0 audio pll generate system clock as 256fs from lrclk figure 13. cpu bu26156 lrclk bclk sdin sdout mclki cpu cpu bu26156 lrclk bclk sdin sdout mclki bu26156 lrclk bclk sdin sdout mclki
datasheet datasheet 17/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 when pll is not used. please generate audio clock on the cpu and supply to t he lsi when pll is not used. then cpu and the lsi are synchronized. case 2: mst=?0?, mclkoe=?0? audio clock is generated by the cpu and supplied to mclki pi n of the lsi. lrclk and bclk are also provided from the cpu. figure 14. cpu bu26156 lrclk bclk sdin sdout mclki clock cpu cpu bu26156 lrclk bclk sdin sdout mclki bu26156 lrclk bclk sdin sdout mclki clock
datasheet datasheet 18/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 serial audio interface the lsi supports sai formats. wsli=?0?, dlyi=?0?, fmti=?0? figure 15. wsli=?1?, dlyi=?0?, fmti=?0? figure 16. wsli=?0?, dlyi=?1?, fmti=?0? figure 17. wsli=?1?, dlyi=?1?, fmti=?0? figure 18. 1 2 3 16 1 2 3 16 left left right sai_ lrclk sai_sdin sai_sdout sai_bclk msb 2sb 3sb l s b msb 2sb 3sb l s b msb 2sb 3sb right 1 2 3 16 1 2 3 16 left left msb 2sb 3sb l s b msb 2sb 3sb l s b msb 2sb 3sb sai_ lrclk sai_sdin sai_sdout sai_bclk left msb 2sb 3sb l s b right 1 2 3 16 1 2 3 16 left msb 2sb 3sb l s b msb 2sb 3sb sai_ lrclk sai_sdin sai_sdout sai_bclk 1 2 3 16 1 2 3 16 left right left msb 2sb 3sb l s b msb 2sb 3sb l s b msb 2sb 3sb sai_ lrclk sai_sdin sai_sdout sai_bclk
datasheet datasheet 19/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 dlyi=?0?, fmti=?1? flame synchronous transfer mode: r channel data is transferred right after l channel data. figure 19. dlyi=?1?, fmti=?1? flame synchronous transfer mode: r channel data is transferred right after l channel data. figure 20. - related register sai transmitter control register sai receiver control register right 1 2 3 16 1 2 3 16 left left msb 2sb 3sb l s b msb 2sb 3sb l s b msb 2sb 3sb sai_ lrclk sai_sdin sai_sdout sai_bclk 1 2 3 16 1 2 3 16 left right left sai_ lrclk sai_sdin sai_sdout sai_bclk msb 2sb 3sb l s b msb 2sb 3sb l s b msb 2sb 3sb
datasheet datasheet 20/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 2 wire serial interface this lsi has 2 wire serial interfaces. the lsi operates as a slave device. the address is fixed at ?0011010?. - format the followings are the protocol of the lsi. write (msb first) start condition (set sda level from ?h? to ?l? during scl=?h?) slave address (0011010) +w (0) (8bit) write address (8bit) write data (8bit) ? stop condition ( set sda level from ?l? to ?h? during scl=?h?) read (msb first) start condition slave address (0011010) +w (0) (8bit) read address (8bit) (stop condition) start condition slave address (0011010) +r (1) (8bit) read data (8bit) the following shows the wave form of the lsi. the yellow gridding shows that slave device drives the bus. the symbol in the wave form means as following table. unit description w/r 0: write 1: read a 0: ack(acknowledge) 1: nak(not acknowledge) a[7-0] address (8bit) d[7-0] data(8bit) write a scl start sda 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 continued from the above 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 8 1 2 3 4 5 6 7 sto p 0 slave address reception a ccess address reception write data reception write data reception write data reception write data reception 0 w a 7 a6 a5 a 4 a 3 a 2 a 1 a 0 a d 7 d 6 d 5 d 4 d 3 d 2 d1 d 0 0 1 1 0 0 1 a a a a a internal write d 7 d 6 d 5 d 4 d 3 d 2 d1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d1 d 0 internal write internal write figure 21. in case there is no stop or start condition after internal regi ster is written (above figure: internal write), the slave device becomes continuous write mode and the next received 8 bits of data will be written into the internal register addressed by incremented by two to the current address.
datasheet datasheet 21/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 read s tar t scl sda 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 0 sta r t a internal read 1 2 3 4 5 6 7 8 0 slave address reception a ccess address reception slave address reception read data transmission read data transmission s r 0 w a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 a a a 0 1 1 0 0 0 1 1 continued fr om the above 0 1 0 1 0 a d7 d6 d5 d 4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 internal read figure 22. if the master device returns ack (acknowledge) after the 8 bi t data transferred from the lsi becomes continuous read mode. the next received 8 bits of data will be read from the internal register addressed by incremented by two to the current address.
datasheet datasheet 22/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 analog block gain diagram figure 23. splm splp sprm sprp hpoutr hpoutl lrclk bclk sdin sdout lin2r lin1r lin2l lin1l minm minp serial audio interface lin3r lin3l adc dac mic input malcmxgain (0xbe/0xbf) 0 +35.25db / 0.75db step malc on/off malcen (0xba/0xbb) limit level 0dbv ( =1vrms)fixed adc input full scale level line input lalcmxgain (0xc8/0xc9) -9.0 +6.0db / 0.75db step lalc on/off lalcen (0xc4/0xc5) limit level 0dbv ( =1vrms)fixed adc input full scale level adc dac vol vol mixvol spvol (0x3a/0x3b) -56 +6.0db speaker output spmixg(0x52/0x53) 0 / +6 / +12 / +18db (analog) (digital) 0dbv 0dbfs (digital) (analog) 0dbfs 0dbv vol vol line output hpvol ([mapcon1]0x36/0x37) -6 / 0 / +3 / +6db vol vol ab/d ab/d hp hp beep input 0db beepin splm splp sprm sprp hpoutr hpoutl lrclk bclk sdin sdout lin2r lin1r lin2l lin1l minm minp serial audio interface serial audio interface lin3r lin3l adc adc dac dac mic input malcmxgain (0xbe/0xbf) 0 +35.25db / 0.75db step malc on/off malcen (0xba/0xbb) limit level 0dbv ( =1vrms)fixed adc input full scale level line input lalcmxgain (0xc8/0xc9) -9.0 +6.0db / 0.75db step lalc on/off lalcen (0xc4/0xc5) limit level 0dbv ( =1vrms)fixed adc input full scale level adc adc dac dac vol vol vol vol mixvol spvol (0x3a/0x3b) -56 +6.0db speaker output spmixg(0x52/0x53) 0 / +6 / +12 / +18db (analog) (digital) 0dbv 0dbfs (digital) (analog) 0dbfs 0dbv vol vol vol vol line output hpvol ([mapcon1]0x36/0x37) -6 / 0 / +3 / +6db vol vol vol vol ab/d ab/d ab/d ab/d hp hp hp hp beep input 0db beepin
datasheet datasheet 23/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 state transition regarding sai input and output control. the following shows state transition about sound control. a change state is carried out by recplay bit setup. figure 24. (1) stop state (recplay=0x0) sound activity is stopped. (2) [adc sai] state (recplay =0x1) analog input signal (mic input/line input) is convert ed to digital data and outputted from sai terminals. (3) [sai dac] state (recplay =0x2) digital signal from sai is converted to analog data and it is outputted from speaker or line amplifier. (4) [adc dac] state (recplay =0x7) analog input signal (mic input/line input) is converted to digi tal data and outputed speaker or line amplifier through dac. (5) [adc dac & sai] state (recplay =0x3) analog input signal (mic input/line input) is converted to digital data and outputed from sai terminals. at one time, digital signal inputted from sai is converted to analog data and it is outputted from speaker or line amplifier. set this state for using sdin to sd out path when lindacen bit enable. *please don?t use ?dac output to limix path? with path (4) and path (5). stop state [sai dac]state [adc dac]state [adc dac&sai]state [adcsai] state 0x0 0x1 0x2 0x3 0x7
datasheet datasheet 24/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 signal flow adc used signal flow figure 25. name function related register setting mic alc micvol analog microphone volume and alc mic alc control mic alc max gain analog input power management 0db to +35.25db, 0.75db step linein alc linvol analog line input volume and alc line alc control line alc max gain analog input power management -15 to +0db, 1db step lin mix mixing the line input, mic input and outputted signal from dac line in control analog path control analog input control.from mic, line and dac. mixing control adc 24bit ad converter analog input power management adc enable/disable l/r select adc(lch/rch) to audio bass [ i2sl / i2sr / monorec] record l/r balance volume control -6.0db to 6.0db(0.1step) hpf1 high path filter for dc cut dsp filter function e nable hpf enable/disable l/r balance l/r bal ance volume control [ rbvoll / rbvolr ] record l/r balance volume control -6.0db to 6.0db(0.1step) hpf2 high pass filter for adc dsp filter function enable high pass filter2 cut-off control hpf enable/disable setting order setting cut-off frequency setting filter sound filters setting sound effect mode dsp filter function enable eq band n gain setting programmable eq band n coeffeicient-a0/1 sound effect mode setting. each filters enable/disable. each filter gain settings. each sound effects characteristics setting lpf programmable lpf setting for adc rec programmable lpf setting rec programmable lpf cutoff coef lpf enable/disable setting order setting. cut-off frequency setting ralcvol digital boost volume for adc recording digital boost volume register -12.000d to 35.625db(0.375step) rdvol digital attenuator and fader for adc record digital attenuator control digital volume control function enable mixer & volume control volume setting -71.5db to 0db (0.5dbstep) fader enable/disenable setting (working together dvmute) *filter block can be used for either adc path or dac path. for example, if filter block is connected to dac, adc is not effected by filter. regarding the detail of register setting, pleas e refer to selection of [semode] register. adc hpf1 l/r balance hpf2 *1 filter lpf *1 rdvol serial audio if dv mute *1 exclusive use malc lalc from mic from line mic vol lin vol filter block lin mix l/r select from dac ralc vol adc hpf1 l/r balance hpf2 *1 filter lpf *1 rdvol serial audio if dv mute *1 exclusive use malc lalc from mic from line mic vol lin vol filter block lin mix l/r select from dac ralc vol
datasheet datasheet 25/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 dac used singal frow figure 26. name function related register setting l/r mix lch/rch mixer for sai input signal mixer & vo lume control mixer setting effect vol digital volume in front of sound effect blocks. playback effect volume -71.5db to 0db (0.5dbstep) stereo enhancer stereo enhancer. stereo gain 3d effect filter each sound filters are enabled. sound effect mode dsp filter function enable eq band n gain setting programmable eq band n coeffeicient-a0/1 sound effect mode setting. each filters enable/disable each filters gain setting each sound effects characteristics setting lpf programmable lpf for dac path. play programmable lpf setting play programmable lpf cutoff coef hpf enable/disable setting order setting cut-off frequency setting palc palcvol digital playback alc and volume playback alc attack time control playback alc decay time control playback target level control playback alc min gain control playback alc volume control playback alc zerocross timeout playback limiter fast release setting alc operation settings pdatt digital attenuator for dac path. fader for noise reduction at changing the digital volume playback digital attenuator control digital volume control function enable mixer & volume control volume setting -71.5db to 0.5db (0.5dbstep) fader on/offsetting fade time setting soft clip softclip limiter for output suppression soft clip enable soft clip threshold soft clip gain softclip enable/disable threshold level, gain setting dac 24bit da converter dac po wer management dac enable/disable mix1 mixing dac output and analog input. speaker amplifier output control 2 gain setting mixing paths setting spvol analog volume for dac to analog output path. speaker amplifier volume control amplifier volume fader control amplifier volume control function enable volume setting -54 to +6db fader on/off setting fade time setting spmixg analog volume for speaker output path speak er amplifier output control 1 gain setting mix2 mixing speaker output signal and beepin input signal. spamp input control beepin amp control mixing paths setting mix3 mixing headphone output signal and beepin input singlal. spamp input control beepin amp control mixing paths setting hpvol analog volume for headphone output path headphone output gain setting gain setting *filter block can be used for either adc path or dac path. for example, if filter block is connectd to dac, adc is not effcetd by filter. regadrding the detail of register setting, pleas e refer to selection of [semde] register. dac pdatt lpf filter effect vol l/r mix serial audio if dv mute stereo enhancer av mute to speaker to headphone filter block soft clip mix1 spvol from mic from line *1 exclusive use palc vol palc to lin mix mix2 mix3 spmixg from beepin spmute *2 hpvol *2 class-d only dac pdatt lpf filter effect vol l/r mix serial audio if dv mute stereo enhancer av mute to speaker to headphone filter block soft clip mix1 spvol from mic from line *1 exclusive use palc vol palc to lin mix mix2 mix3 spmixg from beepin spmute *2 hpvol *2 class-d only
datasheet datasheet 26/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 filter (5bands-programmable iir filter) a five bands equalizer features a second-order iir type band pass filter. volume control of mute, -71.5db+12db (0.5db step) can be controlled at all paths. each channels of the filter can be select ed parallel connection or serial connection the followings are block diagrams at parallel connection and serial connection parallel connection serial connection figure 27. figure 28. the filter coefficient is programmable. from required center frequency and band wi dth, programmable equalizer coefficient-a0 control register and programmable notch filter coefficient-a1 control register value is decided. followings are the setting formula. a0 = (1 - tan f b /fs) / (1 + tan f b /fs) a1 = - 2cos2 f 0 /fs / (1 + tan f b /fs) f0: band center frequency [hz] fb: -3db band width [hz] fs: sampling frequency [hz] * actual setting value is an integral number t hat the result of above formula multiplied by 2 14 then round up numbers of five and above and round down anything under five to an integer. dsp filtering function: on / off dsp filter function enable register can set on or off of each filter function. please chan ge this register when recplay bit is 0x0. if this register is changed on play back or recording, the noise may be generated. stereo enhancer please refer the application note ?s tereoenhancerapplicationnote??. band0 - iir input output coefficient(a0, a1)5ch gain5ch b and1 - iir b and3 - iir b and2 - iir b and4 - iir input output coefficient(a0, a1)5ch gain5ch band0 - iir band1 - iir band2 - iir band4 - iir band2 - iir
datasheet datasheet 27/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 palc (alc fo dac path) function outline the palc adjust a gain automatically from -12db to 35.625db in dac path. a small level singal is made easy listening because the small level signal is amplified to a target level and dynamic range is compressed when the gain setting is a plus gain or palc can be used for a limiter when the gain setting is a minus gain. it protects a speaker from destruction. fast release function makes play sound natural by it release the gain fast when a big singal is suddenly input and a volume drops. operation outline when output waveform level of alc is under the target level, output waveform is increased. maximum level of gain is malcmxgain or lalcmxgain. maximum alc gain is palcvol and minimum level is palcmingain. palcatkc is attack time. it is a time step of decreasing wave form level. palcdcy is decay time. it is a time step of increasing waveform level. these operations are the following. *note:when alc is disable, output signal is also amplified to palcvol gain level. figure 29. input signal maximum gain (palcvol) palc gain palc output target level (palclvl) attack time cycle (palcatk) decay time cycle (palcdcy) minimum gain (palcmingain)
datasheet datasheet 28/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 a peak limiter function is carried in alc. the peak limi tter function short attack time and prevent clipping a wave. a threshold level is fixed at 87.5%(-1.16dbfs) and this func tion is priored the normal alc operation when input level exceed the threshold level. the attack time is a mini mum step, 1/fs, when the peak limiter operates. and this function cannot be turned off. these operations level diagram is the following figure. input (db) output (db) alclvl peak limiter=-1.16dbfs 0d bfs figure 30. alc level diagram zero cross bu26156 combined zerocross function for malc, lalc. zerocross is changed, when input waveform is crossed center level. in case of zero cro ss function is not occurred, bu26156 changes gain when time set by palczctm is passed bu26156 also changes gain past that time when zerocross is enable (zcen=0x0). it is often caused pop noise to change gain without zero cross. alcatk alcatk gain changing at zerocross output signal alc gain alcatk alczctm figure 31. note:it is possible that a noise of changi ng the gain occur when zcen is disable.
datasheet datasheet 29/92 BU26156RFS tsz02201-0v1v0e502570-1-2 ? 2014 rohm co., ltd. all rights reserved. jul.1.2014 rev.001 www.rohm.co.jp tsz22111 ? 15 ? 001 fast release in case of input impulse waveform is over target level of alc, fast release function detects impulse waveform and lsi is returned until normal wave form level quickly. as result of quick return, output waveform of lsi is kept natural sound. -4 -3 -2 -1 0 1 2 3 4 0 10 20 30 40 50 60 70 80 90 10 0 11 0 120 figure 32. not fast release waveform and fast release waveform palcfren bit is setted enable of fast release function. when impulse waveform is over threshold of palcfrth level, fast release function is started and is retur ned waveform until detected level by fast release decay time. this decay time is selected palfrsp bit. waveform is low level not use fast release a ttack return to normal release a ttack release time of fast release quick return from low level waveform input waveform output waveform inpulse waveform output waveform |